Clock tree network in a field programmable gate array

ABSTRACT

A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of co-pending U.S. patent application Ser. No. 11/387,636, filed Mar. 22, 2006, which is a continuation of U.S. patent application Ser. No. 10/916,926, filed Aug. 11, 2004, which is a continuation of U.S. patent application Ser. No. 10/448,258, filed May 28, 2003 and issued as U.S. Pat. No. 6,825,690, both of which are hereby incorporated by reference as if set forth herein.

BACKGROUND OF THE SYSTEM

1. Field of the System

The present system relates to field programmable gate array (FPGA) devices. More specifically, the system relates to a clock tree network in an FPGA having a central clock tree distribution cluster that is configured to distribute the root signals from the phase locked loop to the logic clusters through routed clock clusters and hardwired clock clusters.

2. Background

FPGAs are known in the art. An FPGA comprises any number of logic modules, an interconnect routing architecture and programmable elements that may be programmed to selectively interconnect the logic modules to one another and to define the functions of the logic modules. An FPGA is an array of uncommitted gates with uncommitted wiring channels. To implement a particular circuit function, the circuit is mapped into an array and the wiring channels' appropriate connections are programmed to implement the necessary wiring connections that form the user circuit.

A field programmable gate array circuit can be programmed to implement virtually any set of functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from a user's system, through input buffers and through the circuit, and finally back out the user's system via output buffers. Such buffers may provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation or hysteresis.

An FPGA core tile may be employed as a stand alone FPGA, repeated in a rectangular array of core tiles, or included with other devices in a system-on-a-chip (SOC). The core FPGA tile may include an array of logic modules, and input/output modules. An FPGA core tile may also include other components such as read only memory (ROM) modules. Horizontal and vertical routing channels provide interconnections between the various components within an FPGA core tile. Programmable connections are provided by programmable elements between the routing resources.

The programmable elements in an FPGA can be either one-time programmable or re-programmable. Re-programmable elements used in FPGA technologies may comprise transistors or other re-programmable elements as is well known to those of ordinary skill in the art. One-time programmable elements used in FPGA technologies may comprise antifuse devices.

As FPGAs grow in size, on-chip clock distribution becomes increasingly important. Clock skew and clock delay impact FPGA performance and the task of managing clock skew and clock delay with conventional clock trees becomes more difficult in large FPGAs. As such, in large, fast FPGAs, the performance limiting element is often clock delay due to large clock networks. Phase locked loops (PLLs) are used to reduce the clock delays inherent in large FPGAs and, thereby improve performance.

There is a need in the art for a clock network that has the ability to interject an internal signal into the root of the distribution tree, at the center of any tile or per tile row or tile column of logic clusters. There is also a need for a clock network that has the ability to shut off power on unused portions of the clock tree. In addition, there is a need for a clock network that has the ability to balance skew among all points within the clock network.

SUMMARY OF THE SYSTEM

A clock tree distribution network for a field programmable gate array comprises an interface that has a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array that has programmable elements coupling the logic array to a programmable routing architecture and the interface.

A routed clock network selects a signal from between a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network that selects a signal from between a clock signal from the interface and a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of an FPGA core tile 100 as disclosed in the present system.

FIG. 2 is a block diagram of an illustrative FPGA including multiple core tiles 100 as shown as an example in FIG. 1.

FIG. 3 is a simplified schematic diagram showing the PLL interface with the PLL clusters of the present system.

FIG. 4 is a simplified schematic diagram illustrating the hard-wired clock network and the routed clock network in an FPGA having four core tiles as shown in FIG. 2.

FIG. 5 is a simplified schematic diagram illustrating the hard-wired clock network and the routed clock network in an FPGA having sixteen core tiles.

FIG. 6 is a simplified block diagram illustrating a clock tile cluster of FIG. 1.

FIG. 7 is a simplified schematic diagram illustrating the hardwired clock modules and the routed clock modules of FIG. 6.

FIG. 8 is a simplified block diagram illustrating a hardwired clock cluster of FIG. 1.

FIG. 9 is a simplified schematic diagram illustrating in further detail the hardwired clock cluster of FIG. 8.

FIG. 10 is a simplified block diagram illustrating a routed clock cluster of FIG. 1.

FIG. 11 is a simplified schematic diagram illustrating in further detail the routed clock cluster of FIG. 10.

DETAILED DESCRIPTION OF THE DRAWINGS

Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.

FIG. 1 is a simplified block diagram of an FPGA 10 having one core tile 100 incorporating the clock tree network (not shown), as disclosed in the present system. As shown in FIG. 1, core tile 100 comprises an array of logic clusters 110 arranged in rows and columns. As would be apparent to one of ordinary skill in the art, logic clusters 110 further comprise various logic components such as logic modules and flip-flops (not shown). Core tile 100 also comprise a column of routed clock clusters 112, a row of hard-wired clock clusters 114, a clock tile cluster 116, a column of RAM clusters 108 and RAM memory 106. FPGA core tile 100 is surrounded by two rows of input/output (I/O) clusters 104 and I/O banks 102. On the north and south edges surrounding FPGA core tile 100 there are eight phase-locked-loop clusters (PLL clusters) 120. Four PLL clusters 120 are located on the north edge of FPGA core tile 100 and four PPL clusters 120 are located on the southern edge of FPGA core tile 100. The eight PLL clusters 120 located on the northern and southern edges of FPGA core tile 100 replace eight I/O clusters 104. PLL clusters 120 are coupled to two I/O pads located in I/O banks 102. The interface between PLL clusters 120 and I/O banks 102 will be discussed in greater detail below.

FIG. 2 is a block diagram of an illustrative FPGA 10 including multiple core tiles 100 as shown as an example in FIG. 1. As shown in FIG. 2, FPGA device comprises four core tiles 100, though other numbers of tiles are possible. Core tiles 100 are surrounded by I/O clusters 104, PLL clusters 120 and I/O banks 102.

FIG. 3 is a simplified schematic diagram 200 showing the PLL interface 203 with the I/O clusters 222 of the present system. PLL interface 203 comprises PLL cluster 224, PLL cell 218 and a plurality of selection circuits 208, 210, 212, 214 and 216. PLL interface is discussed in greater detail below. As illustrated in FIGS. 1 and 2, four PLL clusters 120 are located adjacent to each other around the median on first and second edges of FPGA core tile 100.

Referring back to FIG. 3, each PLL cell 218 is coupled to two I/O pads 201. I/O pad 201 is coupled to PLL cell 218 through a boundary scan register (BSR) 206, output buffer 203 and input buffer 205. The function of the BSR 206 is to test the circuit to determine if it performs as programmed as is well known to those of ordinary skill in the art.

In addition, I/O pad 201 may be coupled to PLL cell 218 though a plurality of selection circuits. As shown in FIG. 3, for illustrative purposes only, I/O pad is coupled to PLL cell 218 through selection circuits 208 and 210. As those skilled in the art having the benefit of this disclosure will readily realize, any number of selection circuits may be employed or not employed to coupled I/O pads 201 to PLL cell 218. PLL cells 218 are selectively coupled to PLL cluster 220 through selection circuits 212, 214 and 216. As those skilled in the art having the benefit of this disclosure will readily realize, any number of selection circuits may be employed or not employed to couple PLL cluster 220 to PLL cell 218. Coupling PLL cell 218 to I/O pads 200 and PLL cluster 220 through selection circuits 208, 210, 212, 214 and 216 allows for greater signal-selection flexibility. Selection circuits 208, 210, 212, 214 and 216 allow for different input signals to be received through PLL cell 218 from different ones of PLL clusters 220. Selection circuits 208, 210, 212, 214 and 216 also allow for the routing of output signals from PLL cell 218 to adjacent PLL clusters 220.

Two routing buses connect PLL cell 218 directly to PLL cluster 220. Routing bus 226 connects an output of PLL cell 218 directly to PLL cluster 220. Routing bus 224 connects an output of PLL cluster 220 directly to PLL cell 218.

The I/O pads 201 attached to a PLL cluster 120 can be configured for regular functions through the inside I/O cluster 104 if they are not required by PLL cluster 120. I/O clusters 104 are beyond the scope of this disclosure and will not be discussed in detail herein. The path to I/O cluster 104 should be gated by control signals to minimize loading on the clock path. I/O pads 201 may also be configured in all modes available to the regular I/O pads 201 in the same I/O bank. In particular, the REFN and REFP pads can be configured into a differential pair.

PLL cells 218 may share a pair of dedicated pads, pad 202 coupled to an analog power supply and pad 204. Pad 204 is coupled to pad 202 through a decoupling capacitator (not shown) to reduce the jitter of the PLL.

In the present invention, there are a predetermined number of hardwired clock networks and a predetermined number of routed clock networks situated on each FPGA core depending on the size of the FPGA core. A hardwired clock network as described in the present invention is defined as a clock network capable of selecting signals (including both clock signals and local signals from the FPGA routing architecture), routing signals through the hardwired clock network and delivering a signal to a flip-flop module in a logic cluster or an I/O cluster as shown in FIGS. 1 and 2. A routed clock network as described in the present invention is defined as a clock network capable of selecting signals (including both clock signals and local signals from the FPGA routing architecture), routing signals through the routed clock network and delivering signals through a programmable element to either a flip-flop module or a logic module in a logic cluster or an I/O cluster as shown in FIGS. 1 and 2.

Hardwired clock networks and routed clock networks are further defined and discussed in greater detail below. In this illustrative example, there are four hard-wired clocks and four routed clocks. In one embodiment of present invention, the PLL interface blocks, four on the northern edge of the FPGA core 10 and four on a second edge of the FPGA core corresponding with the four PLL clusters 120 located on the north edge of FPGA core tile 100 and four PPL clusters 120 located on the southern edge of FPGA core tile 100 as shown in FIG. 1 are the on-chip clocks of the present system forming the root of the clock network.

As will be discussed in detail below, the hardwired clock network and routed clock network may be essentially the same except for their final distribution branch. The final branch of hardwired clock network connects directly to the clock selection circuits of the flip-flop modules in the logic clusters 110 and I/O clusters 104 as shown in FIGS. 1 and 2. The final branch of the routed clock network comprises an additional horizontal track with programmable elements coupling to the input tracks of the logic modules and flip-flop modules in the logic clusters 110 and I/O clusters 104 as shown in FIGS. 1 and 2. The addition of programmable elements to the routed clock network provides more flexibility to the routed clock network to carry non-clock signals to logic modules. The hardwired clock network is faster, however, it only serves as a clock function to the flip-flop modules.

Each PLL cell 218, pair of dedicated pads, pad 202 coupled to an analog power supply and pad 204, and PLL cluster 220 together form a PLL interface block. The PLL interface block has a root output 223 which forms the basis for each of the eight clock tree networks in the FPGA. The root output selects either (1) the external clock-pad signal, (2) the internal signal from the FPGA core, (3) the clock 1 signal of the PLL of the PLL interface block, (4) the clock 2 signal of the PLL interface block, or (5) the clock 2 signal in the adjacent PLL interface block as the root output signal for the clock network.

For example, arrow 223 indicates where the root signal is inserted and the clock tree network of the present invention begins. Multiple signals may be chosen as the root signal. The root signal may come directly from I/O pad 201 through selection circuit 212. Additionally, the root signal may come from clock 1 or 2 of the same PLL cell 218 or the PLL root may come from clock 1 of the neighboring PLL cell 218. Finally, The root signal may come directly from the FPGA core through I/O cluster 222 when the PLL interjected FPGA clock signal is in turn selected to become the root and distributed over the clock network as the root signal. This process will be discussed in greater detail below. Thus, five signals may be chosen according to the user circuit to be the root signal for the clock tree network.

FIG. 4 is a simplified schematic diagram illustrating the hardwired clock network and the routed clock network in an FPGA having four core tiles as shown in FIG. 2. Hardwired clock tree network 320 comprises hardwired clock 300. The four hardwired clock networks originate from the four PLL block roots on the northern edge of FPGA core 10 as shown in FIG. 1. Hardwired clock tree network 320 distributes clock signals from the PLL root (clock) 300 through the clock network routing structure 302 to the root centers 304 of each FPGA core tile 100. Routed clock tree network 325 comprises routed clock 310. The four routed clock networks originate from the four PLL block roots on the southern edge of FPGA core 10 as shown in FIG. 1. Routed clock tree network 325 distributes clock signals from the PLL root (clock) 310 through the clock network routing structure 312 to the root centers 306 of each FPGA core tile 100.

FIG. 5 is a simplified schematic diagram illustrating the hard-wired clock network and the routed clock network in an FPGA having sixteen core tiles. Similar reference numerals are used to designate similar structures. Hardwired clock tree network 320 comprises hardwired clock 300. The four hardwired clock networks originate from the four PLL block roots on the northern edge of FPGA core 10 as shown in FIG. 1. Hardwired clock tree network 320 distributes clock signals from the PLL root (clock) 300 through the clock network routing structure 302 to the root centers 304 of each FPGA core tile 100. Routed clock tree network 325 comprises routed clock 310. The four routed clock networks originate from the four PLL block roots on the southern edge of FPGA core 10 as shown in FIG. 1. Routed clock tree network 325 distributes clock signals from the PLL root (clock) 310 through the clock network routing structure 312 to the root centers 306 of each FPGA core tile 100.

FIG. 6 is a simplified block diagram illustrating a clock tile cluster 116 of FIG. 1. Clock tile cluster 116 is located in the center of each FPGA core tile 100 as shown in FIG. 1. Clock tile cluster 116 receives the signals from the PLL root (clock) 310 and will be discussed in greater detail below in reference to FIG. 7.

Clock tile cluster 116 comprises four hardwired clock distribution modules 352 and four routed clock distribution modules 354. Clock tile cluster 116 also comprises four routed clock modules 356. As will be discussed in greater detail below, routed clock modules 356 are included in clock tile cluster 116 due to its location within the column of routed clock clusters 112 as clearly seen in FIG. 1.

FIG. 7 is a simplified schematic diagram illustrating the hardwired clock distribution modules 352 and the routed clock distribution modules 354 of FIG. 6. Hardwired clock distribution module 352 comprises a two-input AND gate 406, two-input selection circuit 408 and a buffer 410. The first input of two-input AND gate 406 is programmably coupled through programmable elements 412, 416, 418 to horizontal track 420, ground 422 and Vcc 424 respectively in the row above clock tile cluster 400. In the present disclosure, Vcc is used to define the positive power supply for the digital circuit as designed. As one of ordinary skill in the art will readily recognize, the size of a digital circuit may vary greatly depending on a user's particular circuit requirements. Thus, Vcc may change depending on the size of the circuit elements used. The second input of two-input AND gate 406 is programmably coupled through programmable elements 426, 428, 430 to horizontal track 432, ground signal line 434 or Vcc signal line 436 respectively in the same row as clock tile cluster 400.

In this disclosure, various circuits and logical functions are described. It is to be understood that designations such as “1” and or “0” in these descriptions are arbitrary logical designations. In a first implementation of the invention, or “1” may correspond to a voltage high, while “0” corresponds to a voltage low or ground, while in a second implementation, “0” may correspond to a voltage high, while “1” corresponds to a voltage low or ground. Likewise, where signals are described, a “signal” as used in this disclosure may represent the application, or pulling “high” of a voltage to a node in a circuit where there was low or no voltage before, or it may represent the termination, or the bringing “low” of a voltage to the node, depending on the particular implementation of the invention.

The output of two-input AND gate 406 is coupled to one input of two-input selection circuit 408. The second input of two-input selection circuit 408 is coupled to PLL cluster 220 through PLL hardwired clock signal line 439 to receive the clock root signal from PLL cluster 220. Control input 438 of two-input selection circuit 408 is coupled to ground signal line 422 or Vcc signal line 424 respectively in the row above clock tile cluster 400 through programmable elements 442 and 440 respectively. The output of two-input selection circuit 408 is coupled to the input of buffer 410. Buffer 410 has an output coupled to hardwired clock signal line 444, which is coupled to hardwired clock clusters and will be explained in greater detail below.

Routed clock distribution module 354 comprises a two-input AND gate 450, two-input selection circuit 452 and a buffer 454. The first input of two-input AND gate 450 is programmably couplable through programmable elements 456, 458, 460 to horizontal track 420, ground 422 and Vcc 424 respectively in the row above clock tile cluster 400. The second input of two-input AND gate 450 is programmably couplable through programmable elements 462, 464, 466 to horizontal track 432, ground signal line 434 or Vcc signal line 436 respectively in the same row as clock tile cluster 400. The output of two-input AND gate 450 is coupled to one input of two-input selection circuit 452. The second input of two-input selection circuit 452 is coupled to routed clock signal line 468 the clock root signal from the PLL cluster 220, as shown in FIG. 3. Control input 470 of two-input selection circuit 452 is coupled to ground line 434 or Vcc signal line 436 in the same row as clock tile cluster 400 through programmable elements 472 and 474 respectively. The output of two-input selection circuit 452 is coupled to the input of buffer 454. Buffer 454 has an output coupled to routed clock signal line 476 which is coupled to routed clock clusters and will be explained in greater detail below.

Clock tile cluster 116 controls the tile level clock signals. For example, selection circuit 452 of routed clock distribution module 354 can select a signal from either the routed clock tree signal line 468 or AND gate 450. If selection circuit 452 selects routed clock tree signal line 468, then the routed clock tree signal is routed through to row clock distribution modules 112. Selection circuit 452 can also select a local signal from horizontal track 432 in the same row if programmable element 462 is programmed and Vcc is chosen by programming programmable element 460 or from horizontal track 420 in the row above by programming programmable element 412 and Vcc is chosen by programming programmable element 430. Thus, routed clock distribution module 354 can send a local signal using the routed clock network and shut off the routed clock signal through that tile at the tile level. However, as will be discussed below, on the row level, each routed clock module 602 determines whether to choose a local signal to interject into the routed clock network or to shut off a particular row. Finally, if AND gate has one or both inputs tied to ground and selection circuit 452 chooses AND gate 450, then the clock tree signal line 476 to routed clock modules 354 is shut off to local or clock signals. Again, as will be discussed below, on the row level, each routed clock module 602 determines whether to choose a local signal to interject into the routed clock network or to shut off a particular row.

In the hardwired clock network, selection circuit 408 of hardwired clock distribution module 352 can select a signal from either the hardwired clock tree signal line 439 or AND gate 406. If selection circuit 408 selects hardwired clock tree signal line 439, then the hardwired clock tree signal is routed through to hardwired clock clusters 114. Selection circuit 408 can also select a local signal from horizontal track 432 in the same row as hardwired clock distribution module 352 if programmable element 426 is programmed and Vcc is chosen by programming programmable element 416. Additionally, selection circuit 408 can also select a local signal from horizontal track 420 in the row above hardwired clock distribution module 352 if programmable element 412 is programmed and Vcc is chosen by programming programmable element 430. Thus, hardwired clock distribution module 352 can send a local signal using the hardwired clock network and shut off the hardwired clock signal through that tile at the tile level. However, as will be discussed below, on the column level, each hardwired clock module 506 determines whether to choose a local signal to interject into the routed clock network or to shut off a particular column.

Finally, if AND gate 406 has one or both inputs tied to ground and selection circuit 408 chooses AND gate 406, then the clock tree signal line 444 to hardwired clock modules 506 is shut off to local or clock signals. Again, as will be discussed below, on the column level, each hardwired clock module 506 determines whether to choose a local signal to interject into the hardwired clock network or to shut off a particular column.

FIG. 8 is a simplified block diagram illustrating a hardwired clock cluster 114 of FIG. 1. Hardwired clock cluster 114 comprises two sub clusters 502 and 504. Each sub cluster 502 and 504 further comprise four hardwired clock modules 506. Hardwired clock modules 506 will be discussed in greater detail below.

FIG. 9 is a simplified schematic diagram illustrating in further detail the hardwired clock cluster 114 of FIG. 8. Similar reference numerals will be used to designate similar structures. Hardwired clock cluster 114 comprises two sub clusters 502 and 504. Sub cluster 502 comprises four hardwired clock modules 506. In one embodiment, hardwired clock modules 506 are identical and therefore the connections of only one will be discussed herein. Hardwired clock module 506 in sub cluster 502 comprises a two-input selection circuit 526 and a buffer 528. Two-input selection circuit 526 has a first input coupled to hardwired clock signal line 510. Hardwired clock signal line originates from PLL cluster 220 as set forth above. A second input of two-input selection circuit 526 is coupled to vertical track west 514 through programmable elements 512. Thus, two-input selection circuit 526 may either receive a signal from hardwired clock signal line 510 or vertical track 514. Control input 527 is coupled to ground 518 through programmable elements 516 or Vcc 520 through programmable elements 522. The output of two-input selection circuit 526 is coupled to the input of buffer 528. The output of buffer 528 is coupled to a clock signal line 0 through 3 coinciding with hardwired clock modules 1 through 4. Clock signal lines 0 through 3 provide the signals to all flip-flops (not shown) in logic clusters 110 and I/O clusters 104 in the FPGA core tile 100 as shown in FIG. 1.

Sub cluster 504 comprises four hardwired clock modules 506E. In one embodiment, hardwired clock modules 506E are identical and therefore the connections of only one will discussed herein. Hardwired clock module 506E in sub cluster 502 comprises a two-input selection circuit 530 and a buffer 532. Two-input selection circuit 530 has a first input coupled to hardwired clock signal line 510. Hardwired clock signal line originates from PLL cluster 220 as set forth above. A second input of two-input selection circuit 530 is coupled to vertical track west 534 through programmable elements 536. Thus, two-input selection circuit 530 may either receive a signal from hardwired clock signal line 510 or vertical track 534. Control input 538 is coupled to ground 518 through programmable elements 524 or Vcc 520 through programmable elements 540. The output of two-input selection circuit 530 is coupled to the input of buffer 532. The output of buffer 532 is coupled to a clock signal line 0 through 3 coinciding with hardwired clock modules 1 through 4. Clock signal lines 0 through 3 provide the signals to all flip-flops (not shown) in logic clusters 110 and I/O clusters 104 in the FPGA core tile 100 as shown in FIG. 1.

Hardwired clock modules 506W can be programmed to select a clock signal from hardwired clock signal line 510 from the parent clock tree or to select a local signal from a vertical track or to shut down the column signal line at the column level. For example, to select the clock signal, selection circuit 526 selects the clock signal line 510 and sends the clock signal to all flip-flops in the FPGA tile column. To interject a local signal, selection circuit selects vertical track 514 by programming programmable element 512 and 516 and a localized clock domain is created. To shut down the clock network at the column level, selection circuit 526 can select either ground 518 or Vcc 520 by programming programmable elements 517 or 522 respectively to create a static signal. The programming is substantially the same in hardwired clock modules 506E.

FIG. 10 is a simplified block diagram illustrating a routed clock cluster 112 of FIG. 1. Routed clock cluster 112 comprises four routed clock modules 602. Routed clock clusters 112 comprise a column of clusters located in the center of FPGA core tile 100 as shown in FIG. 1. Routed clock clusters 112 supply the clock signals to all the combinatorial logic in FPGA core tile 100.

FIG. 11 is a simplified schematic diagram illustrating in further detail the routed clock module 602 of FIG. 10. Routed clock module 602 comprises a two-input AND gate 604 with a first input coupled to either horizontal track 636 through programmable element 612, ground signal line 640 through programmable element 614 or Vcc signal line 642 through programmable element 616 in row 644 above routed clock module 602. Two-input AND gate 604 has a second input coupled to either horizontal track 650 through programmable element 622, ground signal line 654 through programmable element 624 or Vcc signal line 656 through programmable element 626 in the same row 646 as routed clock module 602.

Two-input AND gate 604 has an output coupled to an input of two-input selection circuit 606. The second input of two-input selection circuit 606 is coupled to the output signal line 632 of routed clock distribution module 354 as shown in FIG. 7. Two-input selection circuit 606 has a control line 658 coupled to either ground signal line 640 through programmable element 618 or Vcc signal line 642 through programmable element 620. Thus, selection circuit 606 can either choose a signal from the routed clock distribution module 354 or from horizontal track 636 in the row above routed clock module 602 or horizontal track 650 in the same row as routed clock module 602 and route the signal into the routed clock network via routed clock signal line 652 through buffers 608 and 610.

For example, routed clock distribution module 354 can be programmed to select a clock signal from routed clock signal line 632 by programming selection circuit 606 to select the clock signal line 632 and sending the clock signal to all logic modules in the FPGA tile row. To interject a local signal, selection circuit 606 selects AND gate 604. To interject a signal from the row 644 above routed clock module 602, element 612 is programmed to route a local signal from horizontal track 636 and the second input is programmed to Vcc by programming programmable element 626. To interject a signal from the same row 646 as routed clock module 602, element 622 is programmed to route a local signal from horizontal track 650 and the second input is programmed to Vcc by programming programmable element 616.

To shut down the routed clock network at the row level, selection circuit 526 can select AND gate 604 which has inputs tied either ground 642 in the row 644 above routed clock distribution module 354 or ground 654 in the same row 646 as routed clock distribution module 354 by programming programmable elements 612 or 622 respectively. As would be apparent to one of ordinary skill in the art, one can shut off the routed clock network by programming the programmable elements to Vcc and creating a static condition.

As set forth above, the first section of the clock network is from the PLL root to the centers of all the tiles in a chip. The path between the root and the centers of each tile is designed to produce the minimum skew and shortest latency. The chip level clock network design may vary depending on the tile array and organization. However, the chip level clock networks of both the hardwired clock network and the routed clock network are the same but mirror along the east-west axis of the chip. The second section of the clock network distribution of the present invention starts from the center of a tile to a selected set of inputs of the logic clusters.

It should be understood that various alternatives to the embodiments of the disclosed method and apparatus described herein maybe employed in practicing the disclosed method and using the disclosed apparatus. It is intended that the following claims define the scope of the disclosed method and apparatus and that methods and structures within the scope of these claims and their equivalents be covered thereby. 

1. A method for providing a clock tree distribution network for a field programmable gate array (FPGA), said method comprising: providing an interface having a root signal selected from at least one of an external clock signal, an internal clock signal and a plurality of phase lock loop cell output signals, said interface having programmable elements; coupling a logic array to said interface, said logic array having a plurality of local signals and programmable elements; coupling a programmable routing architecture to said programmable elements of said interface and said logic array; providing a routed clock network that selects a signal from at least one of said root signal, a local signal from said logic array, a positive power supply signal, and a ground signal and routes said selected signal to at least one of a plurality of logic modules and a plurality of flip-flops in said logic array; and providing a hardwired clock network configured to select a signal from at least one of said root signal and a local signal from said logic array, a positive power supply signal, and a ground signal and routes said selected signal to said plurality of flip-flops in said logic array. 